1. Field of the Invention
This invention relates to a process and compositions useful for forming conductive paths in and on substrates and packages suitable for thick film or thin film applications. In particular, the compositions are useful for forming both circuit traces and dense vias having high bond strengths, low resistivities, a narrow distribution of resistance values, and high thermal conductances. The traces and vias may also be made hermetic.
2. The State of the Art
Substrates for electronic circuitry are one of the most important applications for high performance ceramics in the microelectronics industry. The circuit traces are applied using thick film and thin film techniques. In the case of single layer substrates, conductors and other trace components (resistors, capacitors, etc.) are positioned on the top and bottom of such substrates, with conductive vias positioned through the substrate for connecting the top and bottom circuitry. The electromechanical property requirements for traces and vias in thick film hybrid circuits are generally not difficult to meet; however, because of the high performance and high costs associated with thin film hybrids, the circuitry, including the vias, has stringent property requirements and must be fabricated with precision. For both traces and vias, two important requirements are low electrical resistance and good bonding/adhesion to the substrate. Further, and particularly regarding thick film circuitry which is co-sintered with the substrate, the shrinkage of the circuit paths must conform to that of the substrate while also developing a strong bond thereto.
Multi-layer metallized ceramic packages are typically constructed from a green tape, generally composed of ceramic particles and an organic binder; the tape layers typically have a thickness ranging from about 5 to about 25 mils. After the tape is cut into sections, metallized trace patterns for circuits and power and ground planes are applied to the surface of the sections, and metallized vias are created through the sections. Thereafter, multiple layers are stacked, laminated under heat and pressure, and the entire structure is sintered to form a monolithic structure having three-dimensional circuitry. The traces form circuit patterns on the surface of a substrate section (including power and ground planes) and the vias interconnect the surface traces on different layers.
The ceramic portion of the tape is typically formed from a combination of approximately 90-96% commercial alumina (crystalline) and 4-10% silicon-based glass. The metallization ink or paste is typically composed of metal particles (such as tungsten, molybdenum, or a combination of molybdenum and manganese), an organic vehicle, and often glass and/or ceramic to promote adhesion of the metallization to the substrate during co-sintering. Glass is usually present in the substrate formulation to promote bonding of the metallization to the substrate and to allow for lower temperature sintering of the substrate, as previously noted. In prior art metallization formulations without glass, such as based on 100% tungsten particles, a glass component would be present in the substrate, which during sintering migrates into the tungsten layer, thereby providing interfacial adhesion between the metallization and the substrate.
Circuit packages produced from typical prior art formulations (i.e., those containing glass) display a dielectric constant of approximately 9-9.5, a thermal conductivity of approximately 0.045 cal-cm/cm.sup.2 -sec-.degree.C. at 20.degree. C. (compared with 0.085 for 99.5% alumina), a shrinkage variability of 0.5%-1.0%, and a surface finish of greater than about 25 microinches. While these substrate properties may have been acceptable for conventional semiconductor packages, they are inadequate for high-performance large scale integration circuitry. Accordingly, there is a need for metallization compositions which exhibit controlled shrinkage and achieve good adhesion during co-sintering; also, the sintered metallization should have a low resistivity and a high bond strength.
Particularly for thin film applications, such as thin film hybrid packages, metallized vias must be formed in the substrates. Thin film substrates are typically 99.5+% alumina in which vias are formed by "drilling" a hole in the substrate, the inside of which is then coated with a thin layer of metal, typically using lithography, vapor deposition methods, or plating processes. Because of the small tolerances required for the hole position (typically .+-.3 mils absolute, or about 1 mil/inch) for thin film processing, laser drilling of the via holes is commonly practiced. Although precise hole position is possible with laser systems, many problems are yet associated with this method. Slag, microcracks, and other defects are often generated in the substrate near the via holes; these defects can degrade the adhesion and quality of the subsequently applied metallization. Also, reproducible, high quality metallization of laser drilled holes is difficult to achieve. In turn, this can result in an unacceptably broad distribution of resistance values for the vias, which is manifest as low process yields. Additionally, the drilling causes residual stresses around via holes. These stresses can be sufficiently large to cause fracture of the substrate during subsequent assembly operations, particularly during soldering. If this occurs in the final assembly steps of an electronic subsystem, such yield losses can be very costly. Although the stresses may be reduced by heat treating laser drilled substrates prior to metallizing, the product quality is still less than desirable.
Lower cost and potentially higher yield methods for forming via holes have been investigated in recent years. One method is the fabrication of prepunched thin film substrates. Thin film substrates are typically fabricated using a doctor blade process to form a green tape, as described above. Holes are punched into the green tape or tape sections prior to sintering using hard tooling or a numerically controlled punch press. Extreme care is required during tape processing to avoid the introduction of surface defects into the final substrate. The manufacturing of defect-free, smooth substrates, suitable for thin film applications, is made more difficult when via holes are punched into the green tape; yet the quality of such holes is usually sufficient to achieve both a significant cost reduction and improvements in subsequent metallization. However, the use of the prepunched via method is limited by the poor accuracy in positioning the via holes in the fired substrate; the current art in tape technology achieves position tolerances in the range of .+-.0.3 to 1.0% (3-10 mil/inch) because of the variabilities in shrinkage during sintering.
Accordingly, there is a need for methods of producing high quality thin film substrates having metallized vias, which vias have a more uniform distribution of and lower resistivities. Such methods should achieve higher yields and lower fabrication costs, and should also leave minimal residual stress in the area of the substrate integral with the via hole. There is also a need for substrates having dense, hermetic vias; although desirable for certain applications, hermeticity is not possible using current art thin film techniques for metallizing vias. It would also be desirable to provide these aspects in substrates having a higher thermal conductance than those currently produced, and to develop methods applicable to thick film substrates.
One proposed approach has been to co-sinter the metallized traces and vias along with the green ceramic tape. As practiced, traces are laid down using screen printing and via holes are filled with a conventional thick film conductor ink, after which the metallized substrate is co-fired in a reducing atmosphere at high temperatures (e.g., 1500.degree. to 1650.degree. C.). Although this method is suitable for thick film substrates (as discussed above, typically composed of 90-96% alumina and 4-10% glass), little success has been demonstrated with co-sintered circuit traces and vias in substrates and packages comprising greater than about 96% alumina.
The principle reason for this failure (or, at best, very limited success), has been the inadequacy of the applied metallization technology. More particularly, current metallization compositions exhibit poor bonding strengths when used in combination with &gt;96% alumina. In fact, the present industry standard for the bond strength of glass-alumina substrates and packages made therewith is generally in the range of about 4 to 6 kpsi (as quoted by Interamics and Kyocera, respectively). These strength characteristics limit the attachment of lead frames, lids, flanges, and other structures which allow for protection of the active device or for interconnections critical to the performance of the substrate or package. In addition, such metallization compositions exhibit high resistivities (greater than about 6.7.times.10.sup.-3 ohm-cm) and low thermal conductivities; these can be cause by porosity in the metallization and/or by the presence of glass in the metal phase, both of which reduce the desired thermal and electrical properties. Also, hermeticity of the metallization has also not been possible. Still further, the technology for shrinkage tolerances required during co-sintering does not yet provide acceptable results; high shrinkage tolerance is required to achieve high yields of substrates having precisely positioned traces and vias (generally, .+-.0.2% is required). Reduction in shrinkage variability from the current art level of 0.5-1.0% is especially important as feature size decreases and would also provide for increased yields. This is because variability in shrinkage prevents precise location of integrated circuit traces, vias, and other device interconnections, as well as increasing the probability for discontinuities and thus necessitating rejecting the product for poor quality. The need for reduction in shrinkage variability extends to both the manufacturer of substrates and the substrate consumer, who require precise positioning of devices and interconnections and, in a few special cases, reliable circuit personalization by thin-film metallization.
Accordingly, there exists a need for a substrate/metallization system with higher bond strengths, greater thermal conductivities, lower shrinkage variability, and a better substrate surface finish, especially for thin film hybrid packages, while also maintaining the desired dielectric, electrical, and mechanical properties.